1. Field of the Invention
The present invention relates to a method and apparatus for driving a display panel. More specifically, the present invention relates to a method and apparatus for driving a display panel with controlled address power.
2. Discussion of the Related Art
FIG. 1 shows a structure of a conventional three-electrode surface-discharge type plasma display panel (PDP). Referring to FIG. 1, address electrode lines A1, A2, . . . , Am, dielectric layers 102 and 110, Y-electrode lines Y1, . . . , Yn, X-electrode lines X1, . . . , Xn, a phosphor layer 112, partition walls 114, and a protective layer 104 are disposed between front and rear glass substrates 100 and 106 of a conventional surface-discharge PDP 1.
The address electrode lines A1, A2, . . . , Am are formed on a front side of the rear glass substrate 106 and covered by the lower dielectric layer 110. Partition walls 114, which partition off a discharge area of each display cell and prevent optical cross-talk between display cells, are formed on the lower dielectric layer 110 in parallel to the address electrode lines A1, A2, . . . , and Am. The phosphor layer 112 is formed on the lower dielectric layer 110 and on the sides of the partition walls 114.
The X-electrode lines X1, . . . , Xn and the Y-electrode lines Y1, . . . , Yn are formed on a rear side of the front glass substrate 100 to be orthogonal to the address electrode lines A1, A2, . . . , Am. Intersections of the address electrode lines A1, A2, . . . , Am and the X-electrode lines X1, . . . , Xn and the Y-electrode lines Y1, . . . , Yn form discharge cells. The X-electrode lines X1, . . . , Xn and the Y-electrode lines Y1, . . . , Yn are formed having transparent electrode portions Xna and Yna and metallic electrode portions Xnb and Ynb. The front dielectric layer 102 covers the X-electrode lines X1, . . . , Xn and the Y-electrode lines Y1, . . . , Yn. The protective layer 104, which protects the PDP 1 from a strong electric field, may be a MgO layer covering the front dielectric layer 102. A gas for forming plasma is sealed in a discharge space 108.
A conventional PDP driving method includes sequentially performing reset, address, and display sustain steps for a unit subfield. In the reset step, display cell charge states are made uniform. The addressing step sets charge states of for selected and non-selected display cells. In the display sustain step, display discharge is performed in selected display cells.
FIG. 2 shows a structure of a conventional apparatus for driving the PDP 1 of FIG. 1. Referring to FIG. 2, the conventional apparatus may include an image processor 200, a logic controller 202, an address driver 206, an X-driver 208, and a Y-driver 204. The image processor 200 converts an external image signal into a digital signal and generates internal image signals, including 8-bit red (R), green (G), and blue (B) image data, a clock signal, and vertical and horizontal synchronous signals. The logic controller 202 generates driving control signals SA, SY, and SX in response to the internal image signal inputted from the image processor 200. The address driver 206 processes the address signal SA to generate and apply display data signals to address electrode lines. The X-driver 208 processes the X-driving control signal SX and applies the result to the X-electrode lines. The Y-driver 204 processes the Y-driving control signal SY and applies the result to the Y-electrode lines.
U.S. Pat. No. 5,541,618 discloses an address-display separation driving method for the PDP 1.
FIG. 3 shows a conventional address-display separation driving method of the Y-electrode lines of the PDP 1 of FIG. 1. Referring to FIG. 3, a unit frame may be divided into eight subfields SF1, . . . , SF8 for time division gray-scale display. Each subfield SF1, . . . , SF8 may be further divided into a reset period (not shown), an address period A1, . . . , A8, and a discharge-sustain period S1, . . . , S8.
In the address periods A1, . . . , A8, display data signals are applied to the address electrode lines (A1, A2, . . . , Am of FIG. 1) and, a corresponding scan pulse is sequentially applied to each Y-electrode line Y1, Y2, . . . , Yn.
In the discharge-sustain periods S1, . . . , S8, display-discharge pulses are alternately applied to the Y-electrode lines Y1, Y2, . . . , Yn and X-electrode lines X1, X2, . . . , Xn to perform display discharges in selected discharge cells.
The PDP's luminance is proportional to the number of discharge-sustain pulses in the discharge-sustain periods S1, . . . , S8 of the unit frame. When one frame used in forming one image is represented as eight subfields and a 256 level gray scale as shown in FIG. 3, different numbers of sustain pulses may be allocated to each subfield at the rates of 1, 2, 4, 8, 16, 32, 64, and 128. Therefore, in order to realize the luminance of a 133 level gray scale, cells may be addressed and discharge sustained for a first subfield period, a third subfield period, and an eighth subfield period.
The number of sustain pulses allocated to each subfield may vary according to weighted values of the subfields in an automatic power control (APC) step. Additionally, the number of sustain pulses allocated to each subfield may be modified considering gamma characteristics or panel characteristics. For example, a gray scale allocated to a fourth subfield may be reduced from 8 to 6, and a gray scale allocated to a sixth subfield may be increased from 32 to 34. Additionally, the number of subfields used in forming one frame may change according to design specifications.
FIG. 4 is a block diagram showing a conventional address APC apparatus. The APC apparatus includes a pixel difference adder 400, a storage unit 402, a gain table 404, and a gain controller 406. The pixel difference adder 400 adds pixel differences, i.e., differences (Aj,i+1−Aj,i) between gray scales of a current and previous pixel in each vertical line in one frame and outputs an addition result. The storage unit 402 delays the input image data IN during one frame. The gain controller 406 multiplies the image data input from the storage unit 402 by a predetermined weighted value, which is obtained by referring to an output of the pixel difference adder 400 and the gain table 404.
Consequently, the conventional address APC unit of FIG. 4 may detect an address power increase for a large sum of pixel differences in each vertical line in one frame, and then multiply the image data by a reduced weighted value to prevent the power increase.
However, the above-described method may not reduce address power in the case of input image data as shown in FIG. 5. In FIG. 5, in a j-th vertical line Aj, there is a small difference between pixels because the image data has values of 192, 193, 194, . . . Thus, with image data having this pattern, an output value of the pixel difference adder 400 of FIG. 4 is may be small, which may result in little difference in weighted values in the address APC step.
However, as shown in FIG. 6, if the image data having this pattern is changed into subfield data, the number of inversions (1→0, 0→1) during addressing may be large, which increases address power. But the conventional address APC step may not be performed on the image data having this pattern.